1. Field of the Present Invention
The present invention relates to a semiconductor device provided with a memory unit capable of writing, reading and erasing data electrically, and a semiconductor device provided with a nonvolatile memory element as a memory unit.
2. Description of the Related Art
The market is expanding for nonvolatile memories in which data can be electrically rewritten and data can be stored even after a power source is turned off. A nonvolatile memory has a structure similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is provided with a region capable of accumulating charges for a long period of time over a channel formation region. The region capable of accumulating charges is also referred to as a floating gate since it is formed over an insulating layer to be isolated from the surroundings. Further, a control gate is provided over the floating gate with the insulating layer interposed therebetween.
A so-called floating gate type nonvolatile memory having such a structure accumulates charges in or discharges charges form a floating gate by a voltage applied to a control gate. In other words, charges are injected to or extracted from the floating gate by a high voltage applied between a semiconductor layer provided with a channel formation region and the control gate. It is said that a Fowler-Nordheim type (F-N type) tunneling current or a thermal electron flows through the insulating layer over the channel formation region at this time. Therefore, the insulating layer is also referred to as a tunnel insulating layer.
Further, a NOR type cell and a NAND type cell are given for a typical cell structure of the floating gate type nonvolatile memory. The NOR type cell has a structure in which one memory element is included in one cell. The NAND type cell has a structure in which a plurality of memory elements connected in series are included in one cell (see Patent Document 1).
A memory device using a nonvolatile memory element is formed applying LSI technology, and a memory array portion in which nonvolatile memory elements are arranged and a peripheral circuit for controlling operation of the memory array portion are formed over one silicon wafer. In erasing operation of a NAND cell, substrate potentials of the memory array portion are varied so that data is erased collectively. Therefore, in a case of employing the NAND cell, it is necessary not to affect the peripheral circuit. Thus, in the conventional LSI technology, it is required that a well (element region) formed over a wafer be separated for each of the memory array portion and the peripheral circuit.
[Patent Document 1] Japanese Published Patent Application No. 2000-058685